1. Field of the Invention
The invention relates to a method and structure for advantageously forming shallow and/or lightly doped source and drain extension regions in semiconductor devices.
2. Description of the Related Art
As integrated circuit manufacturers strive to provide more devices in smaller wafer areas, there is a continuing quest to define and produce transistors having ever-smaller overall cell geometries and that are capable of operating at increasing switching speeds. For the purposes of this disclosure, cell geometry is defined as the two-dimensional surface area required for implementing a single, integral active logic element, typically an N- or P-channel transistor or a pair of complementary transistors. Cell geometry can be distinguished from transistor geometry in that the latter refers to the three-dimensional structure of a single integral logic element.
A great deal of time and effort has been spent on producing the so-called Lightly Doped Drain-Source (LDD) semiconductor device, wherein shallow and/or lightly-doped extension regions are provided near the edges of the gate structure at the point within the transistor where a high degree of electric field strength occurs. Typically, these extension regions are formed adjacent to higher concentration, source/drain semiconductor regions. For purposes of this disclosure, the phrases "source/drain semiconductor region", "source region" or "drain region" may mean any surface conductive regions in a typical semiconductor device where connection is made to elements external to the device.
The typical LDD structure involves providing narrow, self-aligned, lightly-doped impurity regions between the device channel and more heavily doped diffusions of the source/drain regions in the device. It has been repeatedly shown that significant improvement in breakdown voltages, hot electron effects, and short channel threshold effects can be achieved using LDD regions, thereby allowing transistor operation at higher voltages and shorter channel lengths. Indeed, LDD technology is extremely advantageous in sub-micron channel length devices.
Typically, the lightly-doped drain region is more lightly doped and shallower than the source or drain semiconductor region, so as to minimally impact all other electrical characteristics of the drain-to-channel interface and to maximize the corresponding reduction of the electric field strength within the lightly-doped drain region. This reduction in field strength directly reduces the transfer of energy to charge carriers at the oxide/substrate interface with the corresponding reduction in the number of charge carriers injected into the gate oxide.
Typical devices constructed with LDD regions are shown in Ogura, et al. titled "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", IEEE publication, copyright 1980, and U.S. Pat. Nos. 5,257,095, 4,590,663, 4,282,648, and 4,366,613.
In general, the LDD structure can be fabricated using conventional planar silicon-gate processing techniques and optical lithography. One such conventional process for forming LDD regions in an n-channel transistor structure is shown in FIGS. 1-3. In FIG. 1, a gate structure 26 is shown. The structure 26 is formed by providing a p-type silicon substrate 20, and first covering substrate 20 with a thermally grown silicon dioxide layer 22 (or any suitable dielectric layer formed in accordance with well-known techniques). A gate material layer, such as polysilicon layer 24, is next deposited onto the oxide layer 22, and polysilicon layer 24 and possibly oxide layer 22 are patterned, exposed and etched using any conventional photolithographic etching techniques to form gate structure 26. A light implantation of an n type impurity 28 is thereafter provided to form a lightly doped area 30 in the surface layer of the substrate 20. As shown in FIG. 1, the gate structure 26 will block implantation of the n type impurity under the gate structure.
As shown in FIG. 2, spacer regions 32 are formed by depositing a dielectric material (typically silicon dioxide) over the surface of the gate structure 26 and the shallow n- region 30, and anisotropically etching the material (typically with a "dry" or plasma etch). As shown in FIG. 3, a subsequent n+ implant is utilized to form the source/drain regions 34 in p substrate 20. The n+ regions may be more deeply implanted or may become more deep during subsequent diffusions because they are more heavily doped. It should be noted that the LDD regions may be fabricated on both source/drain semiconductor regions, as shown in FIGS. 1-3; however, the benefits of the structure have been shown where the LDD region is formed on only one side of the gate structure, e.g. the drain region. In such cases, a mask may be provided to inhibit LDD formation on one side of gate structure 56.
While the prior art method for implementing the LDD regions in semiconductor devices has proved useful, improved methods are constantly being sought for reducing the production time of devices, and reducing the number of process steps and the complexity of the material required to manufacture such devices.